1. Field of the Invention
The present invention relates to gain amplifiers, and more specifically to improve speed of an amplifier used in analog to digital converters (ADCs).
2. Related Art
Gain amplifiers are often employed to amplify signals. In general, a gain amplifier amplifies an input signal to generate an amplified output signal. For example, gain amplifiers are employed in, but not limited to, Programmable Gain Amplifiers (PGAs), Analog to Digital Converters (ADCs).
An example gain amplifier used in pipeline ADCs is described in U.S. Pat. No. 6,400,301 entitled “Amplifying Signals in Switched Capacitor Environments”, issued Jun. 4, 2002 to Kulhalli et al (hereafter ‘301 patent’), and is incorporated in its entirety into the present application. Only the details of the 301 patent as believed to be relevant to an understanding of the background are provided in this section. For further details, the reader is referred to the 301 patent available from the U.S. Patent Office, www.uspto.gov.
An ADC in the 301 patent is described as containing sample and hold amplifier (SHA) 110, and stages 120-1 through 120-S as depicted in FIG. 1A. SHA 110 samples input signal received on path 134 and holds the voltage level of the sample for further processing. Stages 120-1 through 120-S together convert the voltage level of the sampled input signal received on path 111 into a corresponding N-bit digital code.
Each stage contains active components to have the ability to drive a next stage. In addition, each stage may resolve some of the bits of the digital value sought to be generated. Thus, each stage 120-1 through 120-S generates a P-bit sub-code corresponding to a voltage level of an analog signal received as an input. For example, stage 120-1 converts a voltage level on path 111 to generate a P-bit sub-code on path 121. The output of each stage is provided as an input to next stage, and thus the previous stage drives the next stage. Stage 120-1 drives stage 120-2 since the output of stage 120-1 is provided on path 111 as input to stage 120-2.
Each stage, except last stage 120-S, generates an output signal which represents ((Vi−Vdac)×Gain), wherein Vi represents the voltage level received from previous stage, Vdac equals ((sub-code×Vref)/2P), with P representing the number of bits in the generated sub-code, gain equals 2P, ‘×’ representing a multiplication operation and ‘/’ representing the division operation.
Digital error correction block 130 receives P-bit sub-code from each stage and corrects error in each P-bit sub-code to provide on path 146 the digital code corresponding to the sample received on path 134. The 301 patent discloses the details of the stages, and is summarized below with reference to FIG. 1B.
Stage 120-1 of FIG. 1B is shown containing flash ADC 150, digital to analog converter (DAC) 160, subtractor 170, and gain amplifier 180. Flash ADC 150 converts a sample of an analog signal received on path 111 into a corresponding P-bit sub-code provided on path 156 (contained in path 121 of FIG. 1A, and P is less than N). DAC 160 converts the sub-code received on path 156 into corresponding analog signal (Vdac) on path 167.
Subtractor 170 generates the difference of sample 111 (Vi) and the analog signal received on path 167 (Vdac). Gain amplifier 180 amplifies the difference voltage (Vi−Vdac) with a gain of 2P and is provided on path 112. The signal on path 112 is used to resolve the remaining bits in the N-bit digital code by the next ADC stages.
The details of an example implementation of flash ADC 150 is shown in FIG. 1C, which is shown containing resistors 195-1 through 195-Q and comparators 140-1 through 140-(Q-1), wherein Q equals 2P.
Resistor ladder containing resistors 195-1 through 195-Q of equal resistance values, divides the reference voltage Vref received on path 191 into the Q-1 voltage levels. Each comparator 140-1 through 140-(Q-1) compares the corresponding division of Vref 191 with the voltage level of the input signal received on path 111, and generates the corresponding logical value.
The outputs of the comparators can be used to generate a P-bit sub-code using a decoder (not shown). Alternatively, the results of the comparisons can be provided directly to subtractor 170, and the combination of subtractor 170 and gain amplifier 180 can be implemented using a switched capacitor circuit as described below with reference to FIGS. 2A–2C.
Circuit 190 of FIG. 2A is shown containing pre-amplifier (pre-amp) 210, main-amplifier (main-amp) 220, capacitors 230-1 through 230-6, and switches 240-1 through 240-6 and 250-1 through 250-5. Switches 240-1 through 240-6 are turned on during one phase of a clock signal (S-phase) and switches 250-1 through 250-3 are turned on during another phase of a clock signal (H-phase). Path 205 provides the Vdac (path 167) of one stage via switch 250-1, and path 204 provides the Vdac of the next stage via switch 240-3.
FIG. 2B depicts the status of configuration of circuit 190 during sampling phase (S-phase). During S-phase, pre-amp 210 and main-amp 220 are decoupled (due to open switch 250-2), and main-amp 220 operates as a part of the gain amplifier of the next stage. Capacitor 230-1 samples input signal on path 111 through switch 240-1 and main-amp 220 provides the required input signal to be sampled by capacitor 230-5 of the next stage. Capacitor 230-4 receives DAC input of the next stage on path 240 through switch 240-3 and the charge on capacitor 230-4, which represents a residue voltage (input voltage to be received from next stage−DAC input on path 204) is transferred to capacitor 230-6. Thus the output of main-amp 220 represents the amplified residue voltage to the next stage.
FIG. 2C depicts the configuration of circuit 190 during hold phase (H-phase). During H-phase, pre-amp 210 and main-amp 220 are connected through switch 250-2, and both together amplify the sampled signal in S-phase. However, capacitor 230-1 receives DAC input on path 205 through switch 250-1 and thus the difference of Vdac from the voltage of sampled signal is amplified. The amplified signal is provided as an amplified residue voltage to the next stage. In addition, switch 250-5 is closed and thus the effective capacitance between the input terminal and output terminal of main-amplifier 220 changes compared to the effective capacitance in the sampling phase.
It may be noted that, stage 120-1 resolves bits in both S-phase and H-phase by receiving the corresponding DAC inputs on paths 204 and 205. Due to such resolution, gain amplifier 180 needs to have a high gain since charge redistribution occurs while resolving the bits. Charge redistribution generally requires high gain at least to meet the linearity requirements of the stages in pipeline ADC 100 as is well known in the relevant arts. Charge redistribution occurs in H-phase due to the transfer of charge on sampling capacitor 230-1 to feed back capacitor 230-3.
Similarly, charge redistribution occurs in S-phase also since one end of compensation capacitor 230-4 is connected to receive DAC input 204 and the charge on capacitor 230-4 is transferred on to capacitor 230-6. During H-phase, both pre-amp 210 and main-amp 220 together resolve bits, however, during S-phase, main-amp 220 resolves the bits of the next stage. Thus, main-amp 220 needs to have a high gain.
One problem with such a main-amplifier is that throughput performance/speed (bandwidth) may be reduced due to the high gain requirement.
Another problem with such a main-amplifier is that the output signal of a high gain amplifier may not settle quickly. Faster settling of signals may be required since the output of each stage is used in the next stage. For example, in one embodiment, the S (shown as 270) and H (shown as 280) signals may be generated as in FIG. 2D, and comparators 140-1 through 140-(Q-1) may need to make bit decisions (i.e., generate corresponding outputs) within duration 261 (i.e., before the rising edge of the next S-phase of the clock signal). Performing such a quick conversion enables main-amplifier 220 to resolve the bits of the next stage in the S-phase itself (thereby not requiring additional stages and thus reducing the power consumption).
Accordingly, it may be appreciated that flash ADC 150 may have a limited time (only between the edges of the sample phase and hold phase of the clock signal) to make a bit decision and thus the output of gain amplifier needs to settle to the correct value quickly. Unfortunately, implementation of high gain amplifiers with short settling times may pose challenges.
Furthermore, as the desired throughput performance of an ADC increases, the settling time may need to be further reduced, which may make the approach(es) of the 301 patent deficient for performing amplifications at high speeds (and thus unsuitable for high speed ADCs as well).
At least for reasons such as those described above, what is needed is a method and apparatus which enables implementation of a high speed gain amplifier.
In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the corresponding reference number.